SWAR (SIMD Within A Register)

SWAR — SIMD Within A Register — treats a single machine word as a vector of smaller lanes (e.g. a 64-bit register as 8 bytes or 32 bit-pairs) and operates on all lanes at once with ordinary integer instructions, using carefully chosen masks to stop carries from crossing lane boundaries. It is the data-parallel half of bit-manipulation (the complement to branchless-programming's control-flow trick): one cheap word-wide op does the work of a loop over lanes, with no dedicated SIMD hardware required.

The canonical example — parallel popcount

The constant-time population-count in bit-twiddling-hacks (and hackers-delight) is SWAR: the 0x55555555 / 0x33333333 / 0x0f0f0f0f mask sequence adds bits in 2-bit, then 4-bit, then 8-bit lanes in parallel (a logarithmic-depth tree of masked adds), then a final multiply-and-shift sums the byte lanes. No branches, no table, no per-bit loop — the whole word's bits are counted in ~12 ops.

Where else it shows up

Byte-pattern detection — testing "does this word contain a zero byte / a given byte?" in one word-wide expression (the basis of fast strlen/memchr); a staple of bit-twiddling-hacks.
Parallel add/compare across lanes with mask-isolated carries — packed arithmetic before SSE/NEON.

The other end of the same axis

valyu-billion-scale-vector-index shows what the SWAR idea looks like when the SIMD ISA is available and the volume is industrial. The work is the same shape — one wide register, lanes operated on together, no branches — but the register is a 512-bit ZMM, the lane op is a hardware popcount (VPOPCNTDQ), and the optimisation that mattered was not the arithmetic at all. It was keeping the register loaded: pinning the compared value in a ZMM across a whole batch instead of reloading it per call took the per-operation cost from 10 ns to 6.9 ns, with about 80% of the original cost being bookkeeping rather than arithmetic.

Read against the caveat below, that is a useful correction. "True SIMD superseded SWAR" is right about the instructions and wrong about the skill: the winning move at 512 bits was a register- allocation and loop-shape decision, which is exactly what a SWAR programmer spends their time on.

The standing caveat applies, with a twist

Like the rest of the spoke (branchless-programming's lesson), much classic SWAR is now matched by true SIMD (SSE/AVX/NEON) and dedicated instructions (POPCNT) — hardware caught up. But SWAR's value is more durable here: it needs no SIMD ISA at all, so it still wins on minimal/embedded targets, in portable code, and inside the wide-word inner loops the vector units can't reach. It is the clearest case of bit manipulation as parallelism extracted from plain integer hardware.

bit-manipulation · population-count · hamming-distance · valyu-billion-scale-vector-index · branchless-programming · bit-twiddling-hacks · hackers-delight

SWAR, or real SIMD? (2026-09-10)

The open scope note above has an answer in practice, if not yet in the domain line. turbovec is this spoke's largest source and its scoring path is true SIMD — NEON SDOT/SMMLA, AVX-512 VNNI, vpermb — not SWAR. It arrives here for the same reason valyu-billion-scale-vector-index did: the arithmetic is bit-width-level (2- and 4-bit codes, LUT scans, popcount-class work), and the whole result turns on feeding an instruction the layout it wants. SWAR remains the technique for where SIMD is unavailable; the question the two share — how do you get many small values through one operation — is one subject, and the spoke now holds far more evidence on the SIMD side than the SWAR side.