Input Multiplexing — Maximum Pins with Minimal Resources (Make:)
Chris Wasshuber, Make:, 10 Aug 2026. A survey of six ways to read more switches than you have pins, written from a specific corner: six switches, two GPIO pins left, and a requirement to detect several pressed at once. The techniques and their costs are on input-multiplexing.
Why this source is different for this spoke
The corpus's standing complaint (see synthesis) is that it holds no independent number about anything — three of the four founding sources are vendor or author self-descriptions, and specs here are claims. This article is the first that compares alternatives against each other on stated metrics: noise margin in millivolts, flash consumption in bytes, pins saved, and whether the technique can see two buttons at once. The assumptions are declared (3 V rail, 10-bit ADC, E12 resistor values, ATtiny-class parts with 1–2 kB of flash), which is what makes the numbers checkable by anyone with the same parts.
T2, with one thing named plainly: the winner of the comparison is the author's own design. His five-resistor arrangement for three switches is presented against the conventional four-resistor ladder and beats it on both axes he measures — 124 mV of noise margin against 59 mV, and 94 bytes of flash against 162 — rising to 150 mV with a sixth resistor, and reusing resistors across pins to reach six switches from six resistors. Decoding drops to a right-shift of the ADC value by 7 bits into a 3-bit lookup table, which is where the byte count goes. Verification was on a "miniTesla prototyping system." Nobody else has replicated any of it.
That is not vendor marketing, and it is not nothing: the numbers follow from divider arithmetic a reader can redo. It is still an author grading his own invention, which is the spoke's standing source caution arriving in a form it has not seen before.
What the comparison establishes
- Matrix scanning does not pay at small counts. Six switches as a 2×3 matrix saves exactly one pin. The technique's reputation comes from 4×4 and up, where it saves eight.
- Charlieplexing is the wrong tool for buttons. n(n−1) is a large number on paper, but two pins yield two switches, and the scheme cannot reliably report simultaneous presses at any size.
- The pin-cheapest option is the flash-dearest. An I²C expander costs two lines and 190 bytes to read; on a 1–2 kB part that ratio decides the design.
- Analog solutions move the failure mode rather than removing it. A resistive ladder trades a digital certainty for a voltage gap, and a diode ladder trades it again for a −2 mV/°C thermal drift needing NTC compensation.
Limits
No code is published, only the shape of the decode (an IF-ELSEIF chain for the classic ladder, a lookup table for the author's). The comparison is over one operating point — 3 V, 10-bit ADC, six switches — and neither supply-voltage variation nor resistor tolerance stacking is worked through, though the E12 series is named. Contact bounce, ESD and the behaviour of the analog options over long wire runs go unmentioned.