ESP32
Espressif‘s 2.4 GHz Wi-Fi + Bluetooth combo SoC — the part half the DIY hardware in this wiki is built on, and until now referenced on three pages without one of its own. T1, read from the Series Datasheet v5.3 rather than the product page the source arrived as, which carries positioning and almost no numbers.
What the datasheet says
- CPU: Xtensa 32-bit LX6, single- or dual-core, 240 MHz. TSMC 40 nm.
- Published CoreMark: “1 core at 240 MHz: 539.98 CoreMark; 2.25 CoreMark/MHz” and “2 cores at 240 MHz: 1079.96 CoreMark; 4.50 CoreMark/MHz.”
- Memory: 448 KB ROM, 520 KB SRAM, 16 KB SRAM in RTC, QSPI to external flash/PSRAM (in-package options exist; the die itself carries no user flash).
- Wi-Fi: 802.11b/g/n, 802.11n at 2.4 GHz up to 150 Mbps, WMM, A-MPDU/A-MSDU, four virtual Wi-Fi interfaces, antenna diversity.
- Bluetooth: v4.2 BR/EDR and BLE, +9 dBm transmit, class 1/2/3 without an external PA.
- Power: deep-sleep 10 µA, an ULP coprocessor that runs while the main cores sleep, RTC memory kept powered.
- Security: secure boot, flash encryption, 1024-bit OTP (up to 768 bits for customers), and hardware AES, SHA-2, RSA and RNG.
- Integration: on-die antenna switch, RF balun, PA, LNA, filters and power management — the reason a usable radio node is a chip plus an antenna.
Read against the Pico, the interesting difference is the document
raspberry-pi-pico arrived here minutes earlier, so the pair invites comparison. On raw figures they are closer than the reputation suggests — 520 KB SRAM each (RP2350), 240 MHz against 150 MHz — and they diverge on kind rather than degree: the ESP32 puts a radio and a security block on the die, the RP2350 puts twelve PIO state machines and a choice of instruction set.
What is more useful for this wiki is that the two vendors document different objects.
- Raspberry Pi documents boards. Headers, castellated pads, JST debug connectors, which variant has wireless. The reader is assumed to be assembling something.
- Espressif documents silicon. A CoreMark score, security primitives, a 40 nm process node, an errata reference, and — the tell — a front page listing parts as NRND (“Not Recommended for New Designs”) and one as EOL. The reader is assumed to be designing a product that must still be buildable in five years.
Part-lifecycle status is something no maker-board page in this corpus carries, and it is standard in a silicon datasheet. The same market, two documentation cultures, and each tells you who the vendor thinks is reading.
It half-touches the spoke’s oldest complaint
This wiki’s first growth edge is that vendor specs are unmeasured. Espressif at least publishes a standard benchmark — CoreMark is a defined workload with a published methodology, which is more than a TOPS figure or a clock speed. Raspberry Pi publishes no benchmark at all for the Pico.
That is not the edge closed. A vendor running a standard benchmark on its own part is still self-reported, CoreMark measures integer core throughput and nothing about radio, power or real workloads, and nobody has run the two parts against each other. Two first-party datasheets are not a comparison — they are two vendors’ claims in the same wiki, which is a better position than one and not the measurement.
The family, and the architecture it is leaving
Added 2026-08-08 from the Wikipedia article (T2, en.wikipedia.org/wiki/ESP32), which carries the
lineup and the history the datasheet does not. Everything above stays sourced to the datasheet.
The part described above launched 6 September 2016 as the successor to the ESP8266. What it grew into matters more than the original chip, because the family split along instruction sets:
| core | clock | radio | |
|---|---|---|---|
| ESP32 | Xtensa LX6, 1–2 cores | 240 MHz | Wi-Fi 4, BT 4.2 |
| ESP32-S2 | Xtensa LX7, 1 core | 240 MHz | Wi-Fi 4, no Bluetooth; USB OTG |
| ESP32-S3 | Xtensa LX7, 2 cores | 240 MHz | Wi-Fi 4, BLE; USB OTG |
| ESP32-C2 | RISC-V, 1 core | 120 MHz | Wi-Fi 4, BT 5 |
| ESP32-C3 | RISC-V | 160 MHz | Wi-Fi 4, BT 5 |
| ESP32-C5 | RISC-V, 2 cores | 240 MHz | Wi-Fi 6, Zigbee, Thread |
| ESP32-C6 | RISC-V, 1 core | 160 MHz | Wi-Fi 6, BT 5 |
| ESP32-H2 | RISC-V, 1 core | 96 MHz | BT 5 + mesh, no Wi-Fi |
| ESP32-P4 | RISC-V, 1–2 cores | 360 MHz | image and voice processing |
Xtensa survives only on the original and the S-series. Every letter Espressif has added since is RISC-V, including the fastest part in the family. Xtensa is a licensed proprietary core, so this is a vendor walking off one and onto an open ISA across an entire product line — a larger commitment than a single part.
This spoke already had the architecture question on the table from the other direction. RP2350 boots Arm Cortex-M33 or Hazard3 RISC-V from the same silicon, which this wiki read as the silicon absorbing the ISA choice so the buyer need not make it. Espressif does the opposite: it makes the choice once, at the vendor level, and ships the result as the default. Two answers to one question, and neither vendor argues for it in a document. You read it off the part numbers.
Espressif’s own ESP-IDF framework is what makes that migration cheap downstream. One API covers the ESP32, S, C and H series, so Xtensa to RISC-V is a recompile rather than a rewrite. Arduino-ESP32, MicroPython, CircuitPython, Rust, Espruino and NodeMCU sit alongside it, which is some of why so much of the DIY hardware in this wiki is ESP32-based.
Tiering: T2, encyclopedic coverage of an established product. Where its specs overlap the datasheet they are the weaker source; what it adds is the lineup, the dates and the succession, none of which a single part’s datasheet carries.
Related
microcontroller · raspberry-pi-pico · embedded-systems · iot-protocols · open-hardware · awesome-embedded-iot-security · espressif · awesome-iot